ASIC Verification Engineer

This position is for a verification/RTL development engineer. Conceives and develops solutions to engineering programs through the application of professionally accepted engineering techniques, practices and procedures.

Responsible for definition, design, verification and documentation for ASIC development. Typical duties: Determines architecture design, logic design, and system simulation. Defines module interfaces/formats for simulation. Evaluates all aspects of the process flow from high-level design to synthesis, place and route, and timing and power utilization. Analyzes equipment to establish operation data, conducts experimental tests, and evaluates results. May also review vendor capability to support development.
Works on problems of diverse scope where analysis of data requires evaluation of identifiable factors. Demonstrates good judgment in selecting methods and techniques for obtaining solutions. Normally receives little instruction on day-to-day work, general instructions on new assignments.

Qualifications
Desired skills include knowledge of System Verilog, Vera, VMM, Linux, object-oriented code, and/or tools used for ASIC development and verification. Additional skills that are a plus include code development; documentation; knowledge of USB, SATA, SAS, FC; and experience in C, C , Perl, and TCL. Candidates should have a degree in Electrical Engineering and 0-3 years related experience. *** Local Candidates Only Please - no relocation assistance offered. ***